1. Field
Embodiments of the invention relate to the field of computer systems and more specifically, but not exclusively, to size-based interleaving in a packet-based link.
2. Background Information
Devices of a computer system, such as a hard disk drive, often communicate with the system's central processing unit (CPU) and system memory via a chipset. The chipset may include a memory controller and an input/output controller. Devices of the computer system may be interconnected using various schemes.
A new generation of interconnects, called Peripheral Component Interconnect Express (hereafter referred to as “PCIe”), has been promulgated by the PCI Special Interest Group. PCIe uses high-speed differential signaling and allows for point-to-point communication between devices. Transmissions along a PCIe connection are made using packets.
Devices often make read requests to memory. Some of these read requests are time-sensitive. In today's systems, a latency sensitive memory read request from a device may be delayed by large payload transfers of other traffic streams. If latency to complete these time-sensitive requests increases, devices become inefficient in how well they can utilize the full bandwidth on the PCIe interconnect. This in turn results in overall slowdown of the Input/Output (I/O) subsystem.